library IEEE;
use ieee.std_logic_1164.all;

use work.package_red.all;

entity red is

	generic(N			: integer := 16
		   );
	port(entrada       : in arreglo;
		 sel		   : in std_logic_vector (1 downto 0);
		 salida		   : out arreglo
		 );
end red;

architecture red_arch of red is

	signal imas1 : arreglo;
	signal imenos1 : arreglo;
	signal imas4 : arreglo;
	signal imenos4 : arreglo;

begin
	G1: for i in 0 to (N-1) generate
		mux_array : mux port map(entrada(i), 
								 sel, 
								 imas1((i+1)mod N), 
							     imenos1((i-1) mod N), 
								 imas4((i+4) mod N), 
								 imenos4((i-4) mod N)
								);
		demux_array: demux port map(sel, imas1(i), imenos1(i), imas4(i), imenos4(i), salida(i));
	end generate G1;
	
end red_arch;